Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and non-volatile/flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Each cell in a non-volatile memory device can be programmed/erased so that it is in one of two states. For example, conventionally, cells are programmed/erased as a single bit per cell (e.g., as in the case with a single level cell—SLC) or multiple bits per cell (e.g., as in the case with a multilevel cell—MLC). Each cell's threshold voltage (Vth) determines the data that is stored in the cell. For example, in an SLC, a Vt of 0.5V might indicate a programmed cell while a Vt of −0.5V might indicate an erased cell.
Once a memory cell goes through an erase operation, it is erase verified. The purpose of the erase verify operation is to determine that the cell's Vt is below a maximum voltage level (e.g., −1V). The most straightforward method for performing an erase verify is to apply an erase verify voltage as Vw1 to the memory cell control gate (e.g., via a select line, such as a word line). If the Vt is less than or equal to Vw1, the cell conducts. If Vt is greater than Vw1, the cell does not conduct.
The current causes the bit line voltage to decay and a sense amplifier detects the voltage decay. The rate of voltage decay detected by the sense amplifier determines whether or not the cell's Vt is above or below the erase maximum threshold.
Due to the limitations of the integrated circuit technology, it is difficult to generate a negative voltage for Vw1 in an inexpensive manner. Therefore, this type of erase verify operation is difficult and expensive to perform and is unlikely to be performed in flash memory integrated circuits due to very small profit margins.
The difficulty of the above erase verify operation can be overcome by an inverted read in which the voltage of the bit lines and the source are inverted from that of the conventional read operation. In this type of verify, the saturated bit line voltage, which is a function of the cell's Vt, can be detected and the passing or failing determination can be made. However, this erase verify method experiences problems as well.
Ideally, the read and erase verify operations would employ the same timing and voltages so that memory cell operations can be simplified and uniform. But using an inverted read as the erase verify results in very different operations. The different timing of the erase verify and read operations is illustrated in FIG. 1.
The upper plot of FIG. 1 shows a timing diagram of a typical prior art erase verify operation that is also referred to as an “inverted” read. This plot shows that when the bit line is selected by the “SEL” select signal and the source is biased at VCC, the bit line (BL) voltage is larger for the more erased memory cells.
The lower plot of FIG. 1 shows a typical prior art read operation timing. It is different from the erase verify operation in that the source line is biased at ground and, when the “SEL” signal selects the bit line, the bit line voltage is more negative for a more erased selected memory cell.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved method for verifying an erased state of a memory cell.